The invention relates generally to methods and apparatus for synchronizing display synchronization signals, and more particularly to methods and apparatus for locking a plurality of display synchronization signals among a plurality of display output devices that are outputting display data to a common display device.
Parallel graphics processing systems are known. For example, a plurality of 3D processing engines may be used to render 3D images for video games or other multimedia applications. In such systems, a plurality of graphics processing chips or 3D engines may render different portions of the same image that is output to a common display device. Accordingly, synchronization of display synchronization signals, such as vertical synchronization (VSYNC) and horizontal synchronization (HSYNC) signals must be properly coordinated.
Parallel graphics processing systems may be constructed wherein one graphics chip receives a fixed clock signal from a fixed clock source and another graphics processor receives a variable clock signal from a variable clock source such as a voltage control oscillator (VCO). In such systems, upon power up, both chips attempt to output pixel data to the common display. Typically, a software or hardware based algorithm detects when horizontal and vertical synchronization signals are locked in phase between the two graphics processors. Synchronization is typically performed during normal operation to keep the VCO locked up and to cancel drift. In addition, systems that employ the voltage control oscillator use a charge pump, such as an analog charging circuit, to suitably vary the voltage controlled oscillator to vary the variable clock source to one of the graphics processor to synchronize its vertical synchronization signal and horizontal synchronization with the other graphics processing chip. However, a problem arises since such analog circuits can have long response times and can take up large amounts of integrated circuit space and discrete VCO circuits are expensive. With higher frequency graphics engines and display devices, such systems typically are not properly synchronized. In addition, the voltage control oscillator which is varied through the charge pump, also adjusts other clocks associated with the graphics processor. Since these clocks are being adjusted constantly, the graphics processor whose clock input is a variable clock input has an unstable graphics processing engine which can cause a jitter effect for output images.
Accordingly, it would be desirable to have a method and apparatus for suitably locking a plurality of display synchronization signals among a plurality of display output devices, such as graphics processors, to provide improved image quality at a reduced cost.